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19-1291; Rev 0; 9/97
IF Undersampler
_______________General Description
The MAX1005 is a combined digitizer and reconstruction integrated circuit designed to work in systems that demodulate and modulate communications signals. It integrates IF undersampling and signal synthesis functions into a single, low-power circuit. Its analog-todigital converter (ADC) is used to directly sample or undersample a downconverted RF signal, while its digital-to-analog converter (DAC) recreates the IF subcarrier and transmission data. The MAX1005's ADC is ideal for undersampling applications, due to the analog input amplifier's wide (15MHz) bandwidth. The DAC has very low glitch energy, which minimizes the transmission of unwanted spurious signals. An on-chip reference provides for low-noise ADC and DAC conversions. The MAX1005 provides a high level of signal integrity from a low power budget. It operates from a single power supply, or from separate analog and digital supplies with independent voltages ranging from +2.7V to +5.5V. The MAX1005 can operate with an unregulated analog supply of 5.5V and a regulated digital supply down to 2.7V. This flexible power-supply operation saves additional power in complex digital systems. The MAX1005 has three operating modes: transmit (DAC active), receive (ADC active), and shutdown (ADC and DAC inactive). In shutdown mode, the total supply current drops below 1A. The device requires only 2.4s to wake up from shutdown mode. The MAX1005 is ideal for hand-held, as well as base-station applications. It is available in a tiny 16-pin QSOP package specified for operation over both the commercial and extended temperature ranges.
____________________________Features
o Differential-Input, 5-Bit ADC o Differential-Output, 7-Bit DAC o 15Msps Min Conversion Rate o 25MHz -1dB Full-Power Bandwidth o 44dB SFDR for ADC 39dB at 10.7MHz SFDR (Imaged) for DAC o Internal Voltage Reference o Parallel Logic Interface o Single-Supply Operation (+2.7V to +5.5V) o 0.1A Low-Power Shutdown Mode
MAX1005
______________Ordering Information
PART MAX1005CEE MAX1005EEE TEMP. RANGE 0C to +70C -40C to +85C PIN-PACKAGE 16 QSOP 16 QSOP
__________________Pin Configuration
TOP VIEW
VCCD 1 16 CLK 15 D0 14 D1
________________________Applications
PWT1900 PHS/P Wireless Loops PCS/N
DGND 2 RXEN 3 AIO+ 4 AIO- 5 TXEN 6 AGND 7 VCCA 8
MAX1005
13 D2 12 D3 11 D4 10 D5 9 D6
QSOP
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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IF Undersampler MAX1005
ABSOLUTE MAXIMUM RATINGS
VCCA to AGND ........................................................-0.3V, +6.0V VCCD to DGND ........................................................-0.3V, +6.0V VCCA to VCCD ...................................................................6.3V Digital I/O Pins (D0-D6, CLK, RXEN, TXEN) to DGND .................................-0.3V to (VCCD + 0.3V) or 6.0V (whichever is smaller) Analog I/O Pins (AIO+, AIO-) to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V) AGND to DGND........................................................-0.3V, +0.3V Power Dissipation (TA = +70C) QSOP (derate 5.90mW/C above 70C) ......................470mW Operating Temperature Ranges MAX1005CEE .....................................................0C to +70C MAX1005EEE...................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, <10sec)...........................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = , TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Transmit Full-Scale Output Voltage VOUT VCCA = VCCD = 3.0V VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V 0.7 (Note 5) (Notes 6, 7) PSR VCC_ (A or D or both) = 3.0V 100mVp-p at 100kHz 5 0.2 0.2 AIO+ = AIOVIN VCCA = VCCD = 3.0V VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V VCCA = VCCD = 2.7V to 5.5V 4.5 24 368 2 400 -42 -42 44 44 4.9 4.9 432 -24 67 -50 0.5 736 28 800 39 39 -28 2.4 TRANSMIT DAC DYNAMIC PERFORMANCE (TA = +25C) (Note 2) Spurious-Free Dynamic Range Total Harmonic Distortion plus Noise Wakeup Time Exiting Shutdown Clock Feedthrough DAC Latency Power-Supply Rejection SFDR THD+N tWAKE (Note 3) (Note 4) dBc dBc s dBc CLK period dB SYMBOL N INL DNL CONDITIONS MIN 7 0.2 0.2 1 1 1 864 TYP MAX UNITS Bits LSB LSB LSB mVp-p TRANSMIT DAC DC ACCURACY (Note 1)
TRANSMIT ADC DC ACCURACY (Note 8) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full-Scale Input Range N INL DNL Bits LSB LSB LSB mV
RECEIVE ADC DYNAMIC PERFORMANCE (TA = +25C) (Note 8) Total Harmonic Distortion Spurious-Free Dynamic Range Effective Number of Bits THD SFDR ENOB (Notes 9, 10) (Note 9) (Note 9) dB dB Bits
2
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IF Undersampler
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = , TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Input Full-Power Bandwidth (-1dB) Conversion Rate Wakeup Time Exiting Shutdown Mode Power-Supply Rejection tWAKE PSR VCC_ (A or D or both) = 3.0V 100mVp-p at 100kHz SYMBOL CONDITIONS VIN = 90% of full scale MIN 15 15 0.6 <0.1 2.4 TYP 25 MAX UNITS MHz Msps s LSB
MAX1005
ANALOG INPUT/OUTPUT (AIO+, AIO-) (Note 11) Input Resistance Input Resistance Temperature Coefficient Input Capacitance (Note 6) POWER REQUIREMENTS Supply Voltage VCCA, VCCD RXEN = 1, TXEN = 0, VCCA = VCCD ADC on, DAC off = 3.0V, RXEN = 0, TXEN = 1, CL 12.5pF ADC off, DAC on RXEN = 1, TXEN = 0, VCCA = VCCD ADC on, DAC off = 3.0V, RXEN = 0, TXEN = 1, CL 12.5pF ADC off, DAC on VCCA = VCCD = 3.0V, CL 12.5pF, RXEN = TXEN 2.7 9.0 2.5 4.0 3.0 <0.1 5.5 14.8 mA 3.8 6.4 mA 5.6 5 A V RIN TCRIN CIN Differential between AIO+ and AIOAIO+ or AIO- to GND TA = +25C, differential between AIO+ and AIO1.56 2.00 -2000 4 4 2.44 k ppm/C pF
Analog Supply Current
ICCA
Digital Supply Current
ICCD
Shutdown Supply Current
ICCA + ICD
DIGITAL INPUTS/OUTPUTS (D0-D6, RXEN, TXEN, CLK) (Note 12) Output High Voltage Output Low Voltage Input High Voltage VOH VOL VIH D0-D4, VCCD = 2.7V to 5.5V, ISOURCE = 200A D0-D4, VCCD = 2.7V to 5.5V, ISINK = 50A D0-D6, CLK VCCD = 2.7V to 5.5V VCCD = 2.7V to 5.5V RXEN, TXEN D0-D6, CLK RXEN, TXEN -0.1 VCCD - 1.0 0 0.7VCCD VCCD 0.5 VCCD + 0.1 0.3VCCD 0.5 V VCCD 0.5 V V
Input Low Voltage
VIL
V
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IF Undersampler MAX1005
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = , TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL RXEN, TXEN; VCCD = 2.7V to 3.6V RXEN, TXEN; VCCD = 3.6V to 5.5V Input Capacitance DAC Data Setup Time DAC Data Hold Time CLK Duty Cycle ADC CLK to Output Data Valid Note 1: tDO CL 12.5pF CIN tDS tHOLD CONDITIONS CONDITIONS D0-D6, CLK; VCCD = 2.7V to 5.5V TXEN = RXEN TXEN = 0 and RXEN = 1, or TXEN = 1 and RXEN = 0 TXEN = RXEN TXEN = 0 and RXEN = 1, or TXEN = 1 and RXEN = 0 MIN -1 TYP MAX 7 1 2 1 4 8 5 5 45 13 0.6 0.3 55 20 pF ns ns % ns A UNITS
Input Current
IIN
D0-D6, CLK; TXEN = 1, RXEN = 0 (Note 6) TA = +25C (Note 6) TA = +25C (Note 6)
TIMING CHARACTERISTICS (Data Outputs: RL = 1M, CL = 15pF, TA = TMIN to TMAX, unless otherwise noted.) (Note 12)
TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the EndPoint Linearity method. Note 2: fIN = 4.3MHz digital sine wave applied to DAC data inputs; fCLK = 15MHz. The reference frequency (fREF) is defined to be 10.7MHz (fCLK - fIN). All frequency components present in the DAC output waveform except for fREF and fIN are considered spurious. Note 3: For DAC SFDR measurements, the amplitude of fREF (10.7MHz) is compared to the amplitudes of all frequency components of the output waveform except for fIN (4.3MHz). Note 4: For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of all harmonic and noise components of the output waveform (except for fIN and fREF) to the RMS amplitude of the fREF component. Note 5: Clock feedthrough is defined as the difference in amplitude between the fREF component and the fCLK component when measured differentially from AIO+ to AIO-. Note 6: Guaranteed by design. Not production tested. Note 7: The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to propagate through to the DAC switches. Note 8: RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differentially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method. Note 9: fIN = 10.7MHz, fCLK = 15MHz. Amplitude is 1dB below full-scale. The reference frequency (fREF) is defined to be 4.3MHz (fCLK - fIN). All components except for fREF and fIN are considered spurious. Note 10: Receive ADC THD measurements include the first five harmonics. Note 11: CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are required, then bypass these pins only to VCCA. Note 12: All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are measured to VOH(AC) for rising output signals and to VOL(AC) for falling output signals. The values for VOH(AC) and VOL(AC) as a function of the VCCD supply are shown in the following table: VCCD (V) 2.7 to 3.3 3.3 to 5.5 VOH(AC) (V) VCCD - 1.1 2/3 x VCCD VOL(AC) (V) 0.5 0.5
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_______________________________________________________________________________________
IF Undersampler
__________________________________________Typical Operating Characteristics
(VCCA = VCCD = 3.0V, TA = +25C, unless otherwise noted.)
MAX1005
RECEIVE ADC INTEGRAL NONLINEARITY
MAX1005-01
RECEIVE ADC DIFFERENTIAL NONLINEARITY
MAX1005-02
TRANSMIT DAC INTEGRAL NONLINEARITY
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX1005-03
0.50 0.40 0.30 0.20
0.50 0.40 0.30 0.20 DNL (LSB) 0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50
0.5
INL (LSB)
0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 -15 -12 -9 -6 -3 0 CODE 3 6 9 12 15
-15 -12 -9
-6
-3
0 CODE
3
6
9
12 15
-64
-48
-32
-16
0 CODE
16
32
48
64
TRANSMIT DAC DIFFERENTIAL NONLINEARITY
MAX1005-04
RECEIVE ADC FFT PLOT
MAX1005-05
FULL POWER ANALOG INPUT BANDWIDTH
VIN = 90% OF FULL SCALE
MAX1005-06
0.5 0.4 0.3
30 20 10 AMPLITUDE (dB) 0 -10 -20 -30 -40 -50 -60 -70 fIN = 10.7MHz fCLK = 15MHz 256 POINTS
0 -1 -2 -3 -4 -5 -6 -7
DNL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -64 -48 -32 -16 0 CODE 16 32 48 64
0
1.465
2.930
4.395
5.860
7.325
AMPLITUDE (dB)
0.2
1
10 ANALOG INPUT FREQUENCY (MHz)
100
FREQUENCY (MHz)
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IF Undersampler MAX1005
______________________________________________________________Pin Description
PIN NAME VCCD DGND RXEN Digital Supply Voltage, +2.7V to +5.5V Digital Ground. Connect to digital ground plane. Receive ADC Enable Input. A logic-high level on this input combined with a logic-low level on TXEN enables the receive ADC and disables the transmit DAC. If RXEN = TXEN, the MAX1005 enters its low-power shutdown mode. Positive Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO+ is the positive analog input to the receive ADC. If RXEN = 0 and TXEN = 1, then AIO+ is the positive transmit DAC output pin. Negative Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO- is the negative analog input to the receive ADC. If RXEN = 0 and TXEN = 1, then AIO- is the negative transmit DAC output pin. Transmit DAC Enable Input. A logic-high level on this input combined with a logic-low level on RXEN enables the transmit DAC and disables the receive ADC. If RXEN = TXEN, the MAX1005 enters its lowpower shutdown mode. Analog Ground. Connect to analog ground plane. Analog Supply Voltage, +2.7V to +5.5V Two MSBs for DAC input data. D6 is the MSB. Data Input/Output Pins. If RXEN = 0 and TXEN = 1, then D4-D0 function as the five lower bits of DAC input data, with D0 as the LSB. If RXEN = 1 and TXEN = 0, then D4-D0 function as the five data outputs for the ADC, with D4 as the MSB and D0 as the LSB. In low-power shutdown mode (RXEN = TXEN), D0-D4 should not be externally held high, to prevent excessive input leakage currents. Clock Input. If the receive ADC is active (RXEN = 1, TXEN = 0), the analog input is sampled on the falling edge of clock and the data outputs (D4-D0) are updated on the rising edge of CLK. If the transmit DAC is active (TXEN = 1, RXEN = 0), input data is clocked in on the falling edge of CLK and the DAC output is updated on the rising edge of CLK. The input clock may continue to run when the MAX1005 is shut down (TXEN = RXEN). FUNCTION
1
2 3
4 5
AIO+ AIO-
6 7 8 9, 10
TXEN AGND VCCA D6, D5
11-15
D4-D0
16
CLK
_______________Detailed Description
The MAX1005 is designed to operate with the Maxim PWT1900 (TAG-6) wireless transceiver chipset consisting of the MAX2411 RF transceiver, the MAX2511 IF transceiver, and the MAX1007 power-control/diversity IC. The MAX1005 integrates all the functions of an IF undersampler into a single low-power integrated circuit. It is also well suited for other time-division duplex (TDD) communications systems. This device includes a 7-bit transmit DAC, a 5-bit receive ADC, two internal bandgap references, clock drivers, and all necessary interface and control logic.
Table 1. Transmit DAC Code Table
DAC INPUT DATA 011 1111 000 0000 100 0000 ANALOG OUTPUT +FS 0 -FS
Receive ADC
The 5-bit receive ADC is used to directly sample or undersample a downconverted RF signal. The ADC converts an analog input signal to a 5-bit digital output code in the twos-complement format. Figure 1 shows the ADC transfer function. Analog input signals are applied differentially between AIO+ and AIO-, with a full-scale range of 200mV. An internal amplifier buffers the input signal and drives the comparator array, minimizing loading on the external signal source. The input amplifier has a full-power -1dB bandwidth of at least 15MHz, making this device ideally suited for undersampling applications.
Transmit DAC
The low-side alias frequency (f CLK - fOUT = 10.7MHz) generated by the MAX1005's 7-bit DAC is used to recreate the IF sub-carrier and transmission data in TDD and other communications systems. The DAC accepts CMOS input data in the twos-complement format and outputs a corresponding analog voltage differentially between AIO+ and AIO-. The full-scale output voltage range is typically 400mV. The DAC code table is shown in Table 1.
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_______________________________________________________________________________________
IF Undersampler MAX1005
SAMPLE n SAMPLE n+2
01111 01110
ANALOG INPUT CLK
SAMPLE n+1
00010 OUTPUT CODE 00001 00000 11111 11110 11101
D0-D4 tDO
n-1
n
n+1
Figure 3. Receive ADC Timing Diagram
10001 10000 - FS COM INPUT VOLTAGE (LSB) +FS
Operating Modes
The MAX1005 has three operating modes: transmit, receive, and shutdown. The operating mode is selected by the RXEN and TXEN inputs, as shown in Table 2. In transmit mode, the DAC is active and the ADC is inactive. Power consumption is typically 16.5mW with a 3V supply voltage. In receive mode, the ADC is active and the DAC is inactive. Power consumption in this mode is typically 39mW with a 3V supply voltage. The third mode is shutdown, in which both the DAC and the ADC are inactive. Select this mode by setting RXEN = TXEN at any voltage from DGND to VCCD. In shutdown mode, the CLK input can continue to run without damaging the device and with no significant increase in the typical shutdown supply current specification of 0.1A. When exiting shutdown, the MAX1005 is guaranteed to be operational within 2.4s after TXEN or RXEN is asserted, as shown in Table 2. To prevent supply-current drain due to leakage currents from entering the ADC output bits, the ADC outputs (D0-D4) should not be held high in low-power shutdown mode.
Figure 1. Receive ADC Transfer Function
CLK DAC INPUT n-1 DATA (D0-D6) DAC OUTPUT tDS n tHOLD n-1 n n+1 n+1 n+2
Figure 2. Transmit DAC Timing Diagram
Digital Interface
The DAC has a 7-bit parallel digital interface. Figure 2 shows the timing diagram for the transmit DAC. Digital data is latched into the DAC input register on the falling edge of CLK. On the next rising edge of CLK the data is transferred to the DAC register and the DAC output voltage is updated. The ADC is enabled by setting TXEN = 0 and RXEN = 1. Figure 3 shows the ADC timing diagram. Input data is sampled on the falling edge of CLK, while output data changes state on the rising edge of CLK. This minimizes digital feedthrough and noise while the analog input is being sampled. The ADC output data is applied to the 5-bit parallel output pins (D0-D4), with the MSB at D4.
Table 2. Operating Mode Selection
RXEN 0 0 1 1 TXEN 0 1 0 1 OPERATING MODE Low-power shutdown: ADC and DAC disabled Transmit mode: DAC active, ADC disabled Receive mode: ADC active, DAC disabled Low-power shutdown: ADC and DAC disabled
_______________________________________________________________________________________
7
IF Undersampler MAX1005
Power-Supply Bypassing and Grounding
The MAX1005 has separate analog (VCCA) and digital (VCCD) power-supply connections, as well as separate analog and digital ground connections to minimize coupling of noisy digital signals into the circuit's analog portion. The device will operate with both of these power supplies connected to any voltage between +2.7V and +5.5V. This feature allows the digital circuitry to operate from a regulated logic power supply; this reduces power consumption and maintains compatibility with external logic, while allowing the analog circuitry to operate from an unregulated supply. The analog ground (AGND) and digital ground (DGND) should be tied together close to the device. At no time should the voltage between AGND and DGND exceed 0.3V. The entire board needs good DC bypassing for both analog and digital supplies. Place the power-supply bypass capacitors close to where the power is routed onto board. 10F electrolytic capacitors with low equivalent-series-resistance (ESR) ratings are recommended. For best effective bits performance, minimize capacitive loading at the digital outputs. Keep the digital output traces as short as possible. Bypass each of the VCC_ supply pins to its respective GND with high-quality ceramic capacitors located as close to the package as possible.
________________Functional Diagram
TXEN RXEN VCCA AGND VCCD DGND
DAC BANDGAP REFERENCE VCCA 1k AIO+ 1k
ADC BANDGAP REFERENCE
ADC CLOCK DRIVER
CLK
DAC CLOCK DRIVER 5-BIT FLASH ADC
5 DIGITAL INTERFACE 7 D6-D0
7-BIT DAC AIO-
7
MAX1005
___________________Chip Information
TRANSISTOR COUNT: 2377 SUBSTRATE CONNECTED TO AGND
________________________________________________________Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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